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etrontech em638165 etron technology, inc. no. 6, technology rd. v, science - based indus trial park, hsinchu, taiwan 30077, r.o.c. tel: (886) - 3 - 5782345 fax: (886) - 3 - 5778671 etron technology, inc., reserves the right to make changes to its products and specifications without notice. 4mega x 16 synchronous dram (sdram) preliminary (rev 0.6, 2/2001) features fast access time from clock: 5/6/6/6/7 ns fast clock rate: 166/143/133/125/100 mhz fully synchronous operation internal pipelined architecture 1m word x 16 - bit x 4 - bank programmable mode registers - cas# latency: 2, or 3 - burs t length: 1, 2, 4, 8, or full page - burst type: interleaved or linear burst - burst stop function auto refresh and self refresh 4096 refresh cycles/64ms cke power down mode single +3.3v 0.3v power supply interface: lvttl 54 - pin 400 mil plastic tsop ii package overview the em638165 sdram is a high - speed cmos synchronous dram containing 64 mbits. it is internally configured as 4 banks of 1m word x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). read and write accesses to the sdram are b urst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bankactivate command which is then followed by a read or write command. the em63816 5 provides for programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. an auto precharge function may be enabled to provide a self - timed row precharge that is initiated at the end of the burst sequence. the re fresh functions, either auto or self refresh are easy to use. by having a programmable mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidt h and particularly well suited to high performance pc applications. pin assignment (top view) key specifications em638165 - 6/7/7.5/8/10 t ck3 clock cycle time(min.) 6/7/7.5/8/10 ns t ac3 access time from clk(max.) 5/5.4/5.4/6/7 ns t ras row active time( max.) 42/45/45/48/50 ns t rc row cycle time(min.) 60/63/68/70/80 ns ordering information part number frequency package em638165ts - 6 166mhz tsop ii em638165ts - 7 143mhz tsop ii em638165ts - 7.5 133mhz tsop ii em638165ts - 8 125mhz tsop ii em638165ts - 10 100 mhz tsop ii vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we# cas# ras# cs# ba0 ba1 a10/ap a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc/rfu udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss
etrontech em638165 preliminary 2 rev 0 .6 feb. 2001 block diagram buffer dq0 | dq15 column decoder decoder 1 mx16 cell array (bank #a) column decoder decoder 1 mx16 cell array (bank #c) column decoder decoder 1 mx16 cell array (bank #d) column decoder decoder 1 mx16 cell array (bank #b) control signal generator mode register clocl buffer command decoder clock cke cs# ras# cas# we# udqm ldqm column counter address buffer a0 a11 ba0 ba1 ~ refresh counter clock buffer
etrontech em638165 preliminary 3 rev 0 .6 feb. 2001 pin descriptions table 1. pin details of em638165 symbol type description clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the inter nal burst counter and controls the output registers. cke input clock enable: cke activates(high) and deactivates(low) the clk signal. if cke goes low synchronously with clock(set - up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. cke is synchronous except af ter the device enters power down and self refresh modes, where cke becomes asynchronous until exiting the same mode. the input buffers, including clk, are disabled during power down and self refresh modes, providing low standby power. bank s elect: ba0,ba1 input select the bank for operation. ba1 ba0 select bank 0 0 bank #a 0 1 bank #b 1 0 bank #c ba0,ba1 input 1 1 bank #d a0 - a11 input address inputs: a0 - a11 are sampled during the bankactivate command (row address a0 - a11) and read/write command (column address a0 - a7 with a10 defining auto precharge) to select one location out of the 2m available in the respective bank. during a precharge command, a10 is sampled to determine if all banks are to be precharged (a10 = high). the ad dress inputs also provide the op - code during a mode register set command. cs# input chip select: cs# enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs# is sampled high. cs# provides for external bank se lection on systems with multiple banks. it is considered part of the command code. ras# input row address strobe: the ras# signal defines the operation commands in conjunction with the cas# and we# signals and is latched at the positive edges of clk. when ras# and cs# are asserted "low" and cas# is asserted "high," either the bankactivate command or the precharge command is selected by the we# signal. when the we# is asserted "high," the bankactivate command is selected and the bank designated by bs is tur ned on to the active state. when the we# is asserted "low," the precharge command is selected and the bank designated by bs is switched to the idle state after the precharge operation. cas# input column address strobe: the cas# signal defines the operatio n commands in conjunction with the ras# and we# signals and is latched at the positive edges of clk. when ras# is held "high" and cs# is asserted "low," the column access is started by asserting cas# "low." then, the read or write command is selected by as serting we# "low" or "high."
etrontech em638165 preliminary 4 rev 0 .6 feb. 2001 we# input write enable: the we# signal defines the operation commands in conjunction with the ras# and cas# signals and is latched at the positive edges of clk. the we# input is used to select the bankactivate or precharge com mand and read or write command. ldqm, udqm input data input/output mask: controls output buffers in read mode and masks input data in write mode. dq0 - dq15 input / output data i/o: the dq0 - 15 input and output data are synchronized with the positive edge s of clk. the i/os are maskable during reads and writes. nc/rfu - no connect: these pins should be left unconnected. v ddq supply dq power: provide isolated power to dqs for improved noise immunity. ( 3.3v 0.3v ) v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. ( 0 v ) v dd supply power supply: +3.3v 0.3v v ss supply ground
etrontech em638165 preliminary 5 rev 0 .6 feb. 2001 operation mode fully synchronous operations are performed to latch the commands at the positive edges of clk. table 2 shows the truth table f or the operation commands. table 2. truth table (note (1), (2) ) command state cke n - 1 cke n dqm ba 0,1 a 10 a 0 - 9,11 cs# ras# cas# we# bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x x v l l h l l write and autoprecharge active (3) h x x v h column address (a0 ~ a7) l h l l read active (3) h x x v l l h l h read and autoprecharge active (3) h x x v h column address (a0 ~ a7) l h l h mode register set idle h x x op code l l l l no - operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h clock suspend mode entry active h l x x x x x x x x power down mode entry any (5) h l x x x x h x x x l h h h clock suspend mode exit active l h x x x x x x x x power down mode exit any l h x x x x h x x x (powerdown) l h h h data write/output enable active h x l x x x x x x x data mask/output disable active h x h x x x x x x x note: 1. v=valid x=don't care l=low level h=high level 2. cke n signal is input level when commands are provided. cke n - 1 signal is input level one clock cycle before the commands are provided. 3. these are states of bank designated by bs signal. 4. device state is 1, 2, 4, 8, and full page burst operation. 5. power down mode can not enter in the burst operation. when this command is asserted in the burst cycle, device state is clock suspend mode.
etrontech em638165 preliminary 6 rev 0 .6 feb. 2001 commands 1 bankactivate (ras# = "l", cas# = "h", we# = "h", bas = bank, a0 - a11 = row address) the bankactivate command activates the idle bank designated by the ba0,1 signals. by latching the row address on a0 to a11 at the time of this command, the selected row access is initiated. the read or write operation in the same bank can occur after a time delay of t rcd (min.) from the time of bank activation. a subsequent ban kactivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). the minimum time interval between successive bankactivate commands to the same bank is defined by t r c (min.). the sdram has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back - to - back activation of the four banks. t rrd (min.) specifies the minimum time required between activati ng different banks. after this command is used, the write command and the block write command perform the no mask write operation. cl k addr ess t0 t 1 t2 t3 t n + 3 t n + 4 t n + 5 t n + 6 . .. .. .. .. .. .. . c o m m a n d . .. .. .. .. .. .. . . .. .. .. .. .. .. . n o p n o p n o p n o p ras# - cas# delay ( t rcd ) ras# - ras# delay time ( t rrd ) ras# cycle time ( t rc ) bank a row addr. bank a col addr. bank b row addr. bank a row addr. bank a a c t i v a t e r/w a with au top rec har ge bank b a c t i v a t e bank a a c t i v a t e aut op re ch ar ge be gi n : "h" or "l" bankactivate command cycle (burst length = n, cas# latency = 3) 2 bankprecharge command (ras# = "l", cas# = "h", we# = "l", bas = bank, a10 = "l", a0 - a9 and a11 = don't care) the bankprecharge command precharges the bank disignated by ba signal. the precharged bank is switched from the active s tate to the idle state. this command can be asserted anytime after t ras (min.) is satisfied from the bankactivate command in the desired bank. the maximum time any bank can be active is specified by t ras (max.). therefore, the precharge function must be perf ormed in any active bank within t ras (max.). at the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 prechargeall command (ras# = "l", cas# = "h", we# = "l", bas = don?t care, a10 = "h", a0 - a9 and a11 = don't care) the prechargeall command precharges all banks simultaneously and can be issued even if all banks are not in the active state. all banks are then switched to the idle state. 4 read command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "l", a0 - a7 = column address) the read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the read command is issued. during read bursts, the valid data - out element from the starting column address will be available following the cas# latency after the issue of the read command. each subsequent data - out element will be valid by the next positive clock edge (refer to the following figure). t he dqs go into high - impedance at the end of the burst unless other command is initiated. the burst length, burst sequence, and cas# latency are determined by the mode register, which is already programmed. a full - page burst will continue until terminated ( at the end of the page it will wrap to column 0 and continue).
etrontech em638165 preliminary 7 rev 0 .6 feb. 2001 cl k com ma nd c as # l at en c y= 2 t ck2 , dq's c as # l at en c y= 3 t ck3 , dq's t0 t 1 t2 t3 t4 t5 t6 t7 t8 rea d a nop nop nop nop nop nop nop nop dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 burst read operation (burst length = 4, cas# latency = 2, 3) the read data appears on the dqs subject to the values on the dqm inputs two clocks earlier (i. e. dqm latency is two clocks for output buffers). a read burst without the auto precharge function may be interrupted by a subsequent read or write command to the same bank or the other active bank before the end of the burst length. it may be interrupted by a bankprecharge/ prechargeall command to the same bank too. the interrupt coming from the read command can occur on any clock cycle following a previous read command (refer to the following figure). cl k com ma nd c as # l at en c y= 2 t ck2 , dq's c as # l at en c y= 3 t ck3 , dq's t0 t 1 t2 t3 t4 t5 t6 t7 t8 rea d a rea d b nop nop nop nop nop nop nop dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 read interrupted by a read (burst length = 4, cas# latency = 2, 3) the dqm inputs are used to avoid i/o contention on the dq pins when the interrupt comes from a write command. the dqms must be asserted (high) at least two clocks prior to the write command to suppress data - out on the dq pins. to guarantee the dq pins against i/o contention, a single cycle with high - impedance on the dq pins must occur between the last read data and the write command (refer to the following three figures). if the data output of the burst read occurs at the second clock of the burst write, the dqms must be asserted (high) at least one clock prior to the write command to avoid internal bus contention. read a n o p n o p n o p n o p wr it e b n o p n o p cl k d q m c o m m a n d dq's t0 t 1 t2 t3 t4 t 5 t6 t 7 t8 n o p dout a 0 d i n b 0 din b 1 d i n b 2 must be hi-z before the w rite com mand : "h" or "l" read to write int erval (burst length 3 4, cas# latency = 3)
etrontech em638165 preliminary 8 rev 0 .6 feb. 2001 cl k dq m com ma nd t0 t 1 t2 t3 t4 t5 t6 t7 t8 nop nop nop nop nop nop banka a c t i v a t e di n a 0 di n a 1 di n a 2 di n a 3 1 cl k in te rv al c as # l at en c y= 2 t ck2 , dq's rea d a wr it e a : "h" or "l" read to write interval (burst length 3 4, cas# latency = 2) cl k dq m com ma nd t0 t 1 t2 t3 t4 t5 t6 t7 t8 nop rea d a nop wr it e b nop nop nop di n b 0 di n b 1 di n b 2 di n b 3 c as # l at en c y= 2 t ck2 , dq's nop nop : "h" or "l" read to write interval (bu rst length 3 4, cas# latency = 2) a read burst without the auto precharge function may be interrupted by a bankprecharge/ prechargeall command to the same bank. the following figure shows the optimum time that bankprecharge/ prechargeall command is issu ed in different cas# latency. cl k com ma nd c as # l at en c y= 2 t ck2 , dq's t0 t 1 t2 t3 t4 t5 t6 t7 t8 rea d a nop nop nop nop ac ti va te nop nop precharge c as # l at en c y= 3 t ck3 , dq's dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 addr ess t rp b a n k , col a ba nk (s ) b a n k , r ow read to precharge (cas# latency = 2, 3) 5 read and autoprecharge command (ras# = "h", cas# = "l", we# = "h", bas = bank, a10 = "h", a0 - a7 = column address) the read and autoprecharge comm and automatically performs the precharge operation after the read operation. once this command is given, any subsequent command cannot occur within a time delay of { t rp (min.) + burst length } . at full - page burst, only the read operation is performed in this command and the auto precharge function is ignored.
etrontech em638165 preliminary 9 rev 0 .6 feb. 2001 6 write command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "l", a0 - a7 = column address) the write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. the bank must be active for at least t rcd (min.) before the write command is issued. during write bursts, the first valid data - in element will be registered coincident with the write command. subsequent data elements will be registered o n each successive positive clock edge (refer to the following figure). the dqs remain with high - impedance at the end of the burst unless another command is initiated. the burst length and burst sequence are determined by the mode register, which is already programmed. a full - page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). cl k c o m m a n d t0 t 1 t2 t3 t4 t 5 t6 t 7 t8 din a 3 n o p writ e a n o p n o p n o p n o p n o p n o p n o p din a 0 din a 1 din a 2 dq0 - dq3 the first data element and the write are registered on the same clock edge. extra data is masked. don't care burst write operation (burst length = 4, cas# latency = 1, 2, 3) a write burst without the auto precharge function may be interrupted by a subsequent write, bankprecharge/prechargeall, or read command before the end of the burst length. an interrupt coming from write command can occur on any clock cycle following the previous write command (refer to the following figure). cl k c o m m a n d t0 t 1 t2 t3 t4 t 5 t6 t 7 t8 din b 2 n o p writ e a n o p n o p n o p n o p n o p wr it e b n o p din a 0 din b 0 din b 1 dq's din b 3 1 clk interval write interrupted by a write (burst length = 4, cas# latency = 1, 2, 3) the read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock e dge in which the last data - in element is registered. in order to avoid data contention, input data must be removed from the dqs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). once the read comman d is registered, the data inputs will be ignored and writes will not be executed. cl k com ma nd t0 t 1 t2 t3 t4 t5 t6 t7 t8 nop wr it e a nop nop nop nop nop rea d b nop di n a 0 do n't care dout b 2 dout b 0 dout b 1 dout b 3 di n a 0 do n't care do n't care dout b 2 dout b 0 dout b 1 dout b 3 i np ut d at a fo r th e w ri te i s ma sk ed . in pu t da ta m us t be r em ov ed f ro m th e dq 's a t le as t on e cl oc k cy cl e be fo re t he r ead d at a ap pe ar s on th e ou tp ut s to a vo id d at a co nt en ti on . c as # l at en c y= 2 t ck2 , dq's c as # l at en c y= 3 t ck3 , dq's write interrupted by a read (burst length = 4, cas# latency = 2, 3)
etrontech em638165 preliminary 10 rev 0 .6 feb. 2001 the bankprecharge/prechargeall command that interrupts a write burst wit hout the auto precharge function should be issued m cycles after the clock edge in which the last data - in element is registered, where m equals t wr /t ck rounded up to the next whole number. in addition, the dqm signals must be used to mask input data, start ing with the clock edge following the last data - in element and ending with the clock edge on which the bankprecharge/prechargeall command is entered (refer to the following figure). cl k t0 t 1 t2 t3 t4 t 5 t6 w r i t e c o m m a n d bank (s) r o w n o p n o p pr ech arge n o p n o p a c t i v a t e b a n k c ol n d i n n d i n n + 1 d q m addr ess dq t w r t r p : don't care note: the dqms can remain low in this example if the length of the write burst is 1 or 2. write to precharge 7 write and autoprecharge command (ras# = "h", cas# = "l", we# = "l", bas = bank, a10 = "h", a0 - a7 = column address) the write and autopr echarge command performs the precharge operation automatically after the write operation. once this command is given, any subsequent command can not occur within a time delay of { (burst length - 1) + t wr + t rp (min.) } . at full - page burst, only the write oper ation is performed in this command and the auto precharge function is ignored. cl k com ma nd t0 t 1 t2 t3 t4 t5 t6 t7 t8 nop nop nop nop nop nop nop c as # l at en c y= 2 t ck2 , dq's c as # l at en c y= 3 t ck3 , dq's di n a 0 di n a 1 di n a 0 di n a 1 * * t dal = t wr + t rp * beg in au topre charge ba nk c an b e r ea ct iv at ed at c om pl eti on o f t dal b a n k a ac ti va te wr it e a au top rec har ge t dal t dal burst write with auto - precharge (burst length = 2, cas# latency = 2, 3) 8 mode register set command (ras# = "l", cas# = "l", we# = "l", a0 - a11 = register data) the mode register stores the data for controlling the various operating modes of sdram. the mode register set command programs the values of cas# latency, addressing mode and burst length in the mode register to make sdram useful for a v ariety of different applications. the default values of the mode register after power - up are undefined; therefore this command must be issued at the power - up sequence. the state of pins a0~a9 and a11 in the same cycle is the data written to the mode regist er. one clock cycle is required to complete the write in the mode register (refer to the following figure). the contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are i n the idle state.
etrontech em638165 preliminary 11 rev 0 .6 feb. 2001 r as # t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 cl k cke cs # c a s# we # a 1 1 a 1 0 a 0 - a 9 dq m dq t ck 2 cl oc k mi n. ad dr es s key t rp hi -z prechargeall mode register s et c o mm an d a n y c o mm a nd mode register set cycle (cas# latency = 2, 3) the mode register is divided into various fields depending on functionality. address bs0,1 a11,10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function rfu* rfu* wbl test mode cas latency bt burst length *note: rfu (reserved for future use) should stay ?0? during mrs cycle. burst length field (a2~a0) this field specifies the data length of column access using the a2~a0 pins and selects the burst length to be 2, 4, 8, or full page. a2 a1 a0 burst length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 full page
etrontech em638165 preliminary 12 rev 0 .6 feb. 2001 burst type field (a3) the burst type can be one of two modes, interleave mode or sequential mode. a3 burst type 0 sequential 1 interleave --- addressing sequence of sequential mode an internal column address is performed by increasing the address from the column address which is input to the device. the internal column address is varied by the burst length as shown in the following table. when the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. data n 0 1 2 3 4 5 6 7 - 255 256 257 - col umn address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - n+255 n n+1 - 2 words: burst length 4 words: 8 words: full page: column address is repeated until terminated. --- addressing sequence of interleave mode a column access is started in t he input column address and is performed by inverting the address bits in the sequence shown in the following table. data n column address burst length data 0 a7 a6 a5 a4 a3 a2 a1 a0 data 1 a7 a6 a5 a4 a3 a2 a1 a0# 4 words data 2 a7 a6 a5 a4 a3 a2 a1# a0 data 3 a7 a6 a5 a4 a3 a2 a1# a0# 8 words data 4 a7 a6 a5 a4 a3 a2# a1 a0 data 5 a7 a6 a5 a4 a3 a2# a1 a0# data 6 a7 a6 a5 a4 a3 a2# a1# a0 data 7 a7 a6 a5 a4 a3 a2# a1# a0# cas# latency field (a6~a4) this field specifies th e number of clock cycles from the assertion of the read command to the first read data. the minimum whole value of cas# latency depends on the frequency of clk. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) cas# latency x t ck a6 a5 a4 cas# latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 x x reserved
etrontech em638165 preliminary 13 rev 0 .6 feb. 2001 test mode field (a8~a7) these two bits are used to enter the test mode and must be progr ammed to "00" in normal operation. a8 a7 test mode 0 0 normal mode 0 1 vendor use only 1 x vendor use only write burst length (a9) this bit is used to select the burst write length. a9 write burst length 0 burst 1 si ngle bit 9 no - operation command (ras# = "h", cas# = "h", we# = "h") the no - operation command is used to perform a nop to the sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. 10 burst stop command (ras# = "h", cas# = "h", we# = "l") the burst stop command is used to terminate either fixed - length or full - page bursts. this command is only effective in a read/write burst without the auto precharge function. the terminated read burst ends after a delay equal to the cas# latency (refer to the following figure). the termination of a write burst is shown in the following figure. cl k com ma nd t0 t 1 t2 t3 t4 t5 t6 t7 t8 rea d a nop nop nop nop nop nop nop bu rs t st op c as # l at en c y= 2 t ck2 , dq's c as # l at en c y= 3 t ck3 , dq's dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 th e bu rst e nd s a ft er a de lay e qu al to t he ca s# la te nc y. termination of a burst read operation (bu rst length ?? 4, cas# latency = 2, 3) cl k com ma nd t0 t 1 t2 t3 t4 t5 t6 t7 t8 nop wr it e a nop nop nop nop nop nop bu rs t st op c as # l at e nc y = 2 , 3 dq's di n a 0 di n a 1 di n a 2 do n't care i np ut d at a f or t he w ri t e is m as ke d. termination of a burst write operation (burst length = x, cas# latency = 1, 2, 3)
etrontech em638165 preliminary 14 rev 0 .6 feb. 2001 11 device deselect command (cs# = "h") the device deselect command disables the command decoder so that the ras#, cas#, we# and address inputs are ignored, regardless of whether the clk is enabled. this command is similar to the no operation command. 12 autorefresh command (ras# = "l", cas# = "l", we# = "h",cke = "h", a11 = ?don?t care, a0 - a9 = don' t care) the autorefresh command is used during normal operation of the sdram and is analogous to cas# - before - ras# (cbr) refresh in conventional drams. this command is non - persistent, so it must be issued each time a refresh is required. the addressing i s generated by the internal refresh controller. this makes the address bits a "don't care" during an autorefresh command. the internal refresh counter increments automatically on every auto refresh cycle to all of the rows. the refresh operation must be pe rformed 2048 times within 32ms. the time required to complete the auto refresh operation is specified by t rc (min.). to provide the autorefresh command, all banks need to be in the idle state and the device must not be in power down mode (cke is high in the previous cycle). this command must be followed by nops until the auto refresh operation is completed. the precharge time requirement, t rp (min), must be met before successive auto refresh operations are performed. 13 selfrefresh entry command (ras# = " l", cas# = "l", we# = "h", cke = "l", a0 - a9 = don't care) the selfrefresh is another refresh mode available in the sdram. it is the preferred refresh mode for data retention and low power operation. once the selfrefresh command is registered, all the in puts to the sdram become "don't care" with the exception of cke, which must remain low. the refresh addressing and timing is internally generated to reduce power consumption. the sdram may remain in selfrefresh mode for an indefinite period. the selfrefres h mode is exited by restarting the external clock and then asserting high on cke (selfrefresh exit command). 14 selfrefresh exit command this command is used to exit from the selfrefresh mode. once this command is registered, nop or device deselect com mands must be issued for t rc (min.) because time is required for the completion of any bank currently being internally refreshed. if auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the selfrefresh mode. 15 clock suspend mode entry / powerdown mode entry command (cke = "l") when the sdram is operating the burst cycle, the internal clk is suspended(masked) from the subsequent cycle by issuing this command (asserting cke "low"). the device operation is held intact while clk is suspended. on the other hand, when all banks are in the idle state, this command performs entry into the powerdown mode. all input and output buffers (except the c ke buffer) are turned off in the powerdown mode. the device may not remain in the clock suspend or powerdown state longer than the refresh period (64ms) since the command does not perform any refresh operations. 16 clock suspend mode exit / powerdown mod e exit command (cke= "h") when the internal clk has been suspended, the operation of the internal clk is reinitiated from the subsequent cycle by providing this command (asserting cke "high"). when the device is in the powerdown mode, the device exits t his mode and all disabled buffers are turned on to the active state. t pde (min.) is required when the device exits from the powerdown mode. any subsequent commands can be issued after one clock cycle from the end of this command. 17 data write / output ena ble, data mask / output disable command (dqm = "l", "h") during a write cycle, the dqm signal functions as a data mask and can control every word of the input data. during a read cycle, the dqm functions as the controller of output buffers. dqm is also used for device selection, byte selection and bus control in a memory system.
etrontech em638165 preliminary 15 rev 0 .6 feb. 2001 absolute maximum rating symbol item rating unit note v in , v out input, output voltage - 1.0 ~ 4.6 v 1 v dd , v ddq power supply voltage - 1.0 ~ 4.6 v 1 t opr operating temperature 0 ~ 70 c 1 t stg storage temperature - 55 ~ 125 c 1 t solder soldering temperature (10 second) 255 c 1 p d power dissipation 1 w 1 i out short circuit output current 50 ma 1 recommended d.c. operating conditions (ta = - 40~85 c) symbol parameter min. ty p. max. unit note v dd power supply voltage 3.0 3.3 3.6 v 2 v ddq power supply voltage(for i/o buffer) 3.0 3.3 3.6 v 2 v ih lvttl input high voltage 2.0 ?e 4.6 v 2 v il lvttl input low voltage - 0.3 ?e 0.8 v 2 capacitance (v dd = 3.3v, f = 1mhz, ta = 25 c) symbol parameter min. max. unit c i input capacitance 2 5 pf c i/o input/output capacitance 4 6.5 pf note: these parameters are periodically sampled and are not 100% tested.
etrontech em638165 preliminary 16 rev 0 .6 feb. 2001 recommended d.c. operating conditions (v dd = 3.3v 0.3v, ta = 0~70 c) - 6/7/7.5/8/10 description/test condition symbol max. unit note operating current t rc 3 t rc (min), outputs open i dd1 85 3 precharge standby current in n on - power down mode t ck = 15ns, cs# 3 v ih (min), cke 3 v ih i dd2n 20 3 precharge standby current in non - power down mode t ck = , clk v il (max), cke 3 v ih i dd2ns 15 precharge standby current in power down mode t ck = 15ns, cke v il (max) i dd2p 2 3 precharge standby current in power down mode t ck = , cke v il (max) i dd2ps 1 active standby current in non - power down mode cke 3 v ih (min), cs# 3 v ih (min), t ck = 15ns i dd3n 30 active standby current in non - power down mode cke 3 v ih (min), clk v il (max), t ck = i dd3ns 25 operating current (burst mode) t ck =t ck (min), outputs open, multi - bank interleave i dd4 100 3, 4 refresh current t rc 3 t rc (min) i dd5 130 3 self refresh current v ih 3 v dd - 0.2, 0v v il 0.2v i dd6 1 ma paramete r description min. max. unit note i il input leakage current ( 0v v in v dd , all other pins not under test = 0v ) - 1 1 m a i ol output leakage current output disable, 0v v out v ddq ) - 1 1 m a v oh lvttl output "h" level voltage ( i out = - 2ma ) 2.4 ?e v v ol lvttl output "l" level voltage ( i out = 2ma ) ?e 0.4 v
etrontech em638165 preliminary 17 rev 0 .6 feb. 2001 electrical characteristics and recommended a.c. operating conditions (v dd = 3.3v ? 0.3v, ta = - 40~85 c) (note: 5, 6, 7, 8) - 6/7/7.5/8/10 symbol a.c. parameter min. max. unit note t rc ro w cycle time (same bank) 60/63/68/70/80 t rcd ras# to cas# delay (same bank) 18/20/20/20/24 t rp precharge to refresh/row activate command (same bank) 18/20/20/20/24 ns t rrd row activate to row activate delay (different banks) 12/14/15/20/25 t ras row activate to precharge time (same bank) 42/45/45/48/50 t wr write recovery time 2 t ccd cas# to cas# delay time 1 clk t ck2 cl* = 2 - / - /10/10/13 9 t ck3 clock cycle time cl* = 3 6/7/7.5/8/10 t ch clock high time 2/2.5/2.5/3/3 10 t cl clock low time 2/2.5/2.5/3/3 10 t ac2 cl* = 2 - / - /6/6/7 10 t ac3 access time from clk (positive edge) cl* = 3 5/5.4/5.4/6/7 ns t oh data output hold time 2.5/2.7/3/3/3 9 t lz data output low impedance 1 t hz data output high impedance 5 /5.4/5.4/6/7 8 t is data/address/control input set - up time 1/1.5/1.3/2/2.5 10 t ih data/address/control input hold time 1/0.8/0.8/0.8/0.8 10 t pde power down exit set - up time 6/7/7.5/8/10 * cl is cas# latency. note: 1. stress greater than those l isted under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . inp ut signals are changed one time during t ck . 4. these parameters depend on the output loading. specified values are obtained with the output open. 5. power - up sequence is described in note 11.
etrontech em638165 preliminary 18 rev 0 .6 feb. 2001 6. a.c. test conditions lvttl interface reference level of ou tput signals 1.4v / 1.4v output load reference to the under output load (b) input signal levels 2.4v / 0.4v transition time (rise and fall) of input signals 1ns reference level of input signals 1.4v 3 . 3 v 1 . 2 k w 8 7 0 w 3 0 p f o u t p u t 1 . 4 v 5 0 w o u t p u t 3 0 p f 5 0 w z0= lvttl d.c. test load (a) lvttl a.c. test load (b) 7. transition times are measured between v ih and v il . transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. t hz defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. if clock rising time is longer than 1 ns, ( t r / 2 - 0.5) ns should be added to the parameter. 10. assumed input rise and fall time t t ( t r & t f ) = 1 ns if t r or t f is longer t han 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. power up sequence power up must be performed in the following sequence. 1) power must be applied to v dd and v ddq (simultaneously) when all input signals are held "nop" state and both cke = "h" and dqm = "h." the clk signals must be started at the same time. 2) after power - up, a pause of 200 m seconds minimum is required. then, it is recommended that dqm is held "high" (v dd levels) to ensure dq output is in high impedance. 3) all banks must be precharged. 4) mode register set command must be asserted to initialize the mode register. 5) a minimum of 2 auto - refresh dummy cycles must be required to stabilize the internal circuitry of th e device.
etrontech em638165 preliminary 19 rev 0 .6 feb. 2001 timing waveforms figure 1. ac parameters for write timing (burst length=4, cas# latency=2) b a0 ,1 t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 t ch t cl t ck2 t i s t i s t i h be gin a uto pre cha rge bank a be gin a uto pre cha rge ban k b t i s t i h t i s rax rbx rbx cax rbx cbx ray ray cay raz raz rby rby t rcd t dal t rc t i s t i h t wr t rp t rrd ax0 ax1 ax2 ax3 bx0 bx1 bx2 bx3 ay0 ay1 ay2 ay3 activate c om ma nd bank a write with au top rec har ge c om ma nd bank a activate c om ma nd ban k b write with au top rec har ge c om ma nd ban k b activate c om ma nd bank a write c om ma nd bank a pr ec ha rge c om ma nd bank a activate c om ma nd bank a activate c om ma nd ban k b cl k cke cs # r as # c a s# we # a 1 0 a 0 - a 9 , a 1 1 dq m dq hi-z
etrontech em638165 preliminary 20 rev 0 .6 feb. 2001 figure 2. ac parameters for read timing (burst length=2, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ch t cl t ck2 t i s t i s t i h be gin a uto pre cha rge ban k b t i h t i h t i s rax rax cax rbx rbx cbx ray ray t rrd t r as t rc t rcd t ac2 t lz t oh t hz ax0 ax1 bx0 bx1 t rp activate c om ma nd bank a r e ad c om ma nd bank a activate c om ma nd ban k b re ad w ith au to p rech arge c om ma nd ban k b pr ec ha rge c om ma nd bank a activate c om ma nd bank a hi -z t ac2 t hz
etrontech em638165 preliminary 21 rev 0 .6 feb. 2001 figu re 3. auto refresh (cbr) (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ck2 rax rax cax t rp t rc ax0 ax1 ax2 ax3 pr ec ha rg ea ll c om ma nd aut oref resh c om ma nd aut oref resh c om ma nd activate c om ma nd bank a r e ad c om ma nd bank a t rc
etrontech em638165 preliminary 22 rev 0 .6 feb. 2001 figure 4. power on sequene and auto refresh (cbr) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ck2 high level is r eauired mi nim um o f 2 re fre sh c ycl es are req uir ed hi -z t rp t rc add ress key inp uts m ust be sta ble fo r 200 m s pr ech ar gea ll c om ma nd 1st autoref resh c om ma nd 2n d au to r efre sh c om ma nd mo de r egi ster se t co mma nd any c om ma nd
etrontech em638165 preliminary 23 rev 0 .6 feb. 2001 figure 5. self refresh entry & exit cycle cl k cke cs # r as # c a s# b a0 ,1 a 0 - a 9 , a 1 1 we # dq m t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 dq * note 1 *not e 2 t i s *not e 3 *not e 4 t rc(m in) *not e 7 *not e 5 *not e 6 *not e 8 *no te 8 hi -z hi -z sel f refr esh en ter self refresh exit aut oref resh t s rx t pde note: to enter selfrefresh mode 1. cs#, ras# & cas# with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don't care except for cke. 3. the device remains in selfrefresh mode as long as cke stays "low". once the device enters selfrefresh mode, minimum t ras is required before exit from selfrefresh. to exit selfrefresh mode 1. system clock restart and be stable before returning cke high. 2. enable cke and cke should be set high for minimu m time of t srx . 3. cs# starts from high. 4. minimum t rc is required after cke going high to complete selfrefresh exit. 5. 2048 cycles of burst autorefresh is required before selfrefresh entry and after selfrefresh exit if the system uses burst refresh .
etrontech em638165 preliminary 24 rev 0 .6 feb. 2001 figure 6.1. clock suspension during burst read (using cke) (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t 7 t8 t9 t 10 t 1 1 t1 t 13 t 14 t 15 t 16 t 17 t1 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ck1 rax rax cax hi -z ax0 ax1 ax2 ax3 activate c om ma nd bank a r e ad c om ma nd bank a cl oc k su sp en d 1 cyc le cl oc k su sp en d 2 cycl es cl oc k su sp en d 3 cycl es t hz note: cke to clk disable/enable = 1 clock
etrontech em638165 preliminary 25 rev 0 .6 feb. 2001 figure 6.2. clock suspension during burst read (using cke) (burst length =4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ck2 rax rax cax hi -z ax0 ax1 ax2 ax3 activate c om ma nd bank a r e ad c om ma nd bank a cl oc k su sp en d 1 cyc le cl oc k su sp en d 2 cycl es cl oc k su sp en d 3 cycl es t hz note: cke to clk disable/enable = 1 clock
etrontech em638165 preliminary 26 rev 0 .6 feb. 2001 figure 6.3. clock suspension during burst read (using cke) (burst length=4, cas# latency=3) t0 t 1 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ck3 rax rax cax hi -z ax0 ax1 ax2 ax3 activate c om ma nd bank a r e ad c om ma nd bank a cl oc k su sp en d 1 cyc le cl oc k su sp en d 2 cycl es cl oc k su sp en d 3 cycl es t hz t 2 note: cke to clk disable/ena ble = 1 clock
etrontech em638165 preliminary 27 rev 0 .6 feb. 2001 figure 7.1. clock suspension during burst write (using cke) (burst length = 4, cas# latency = 1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ck1 rax rax cax hi -z dax0 activate c om ma nd bank a write c om ma nd bank a cl oc k su sp en d 2 cycl es cl oc k su sp en d 3 cycl es dax1 dax2 dax3 cl oc k su sp en d 1 cyc le note: cke to clk disable/enable = 1 clock
etrontech em638165 preliminary 28 rev 0 .6 feb. 2001 figure 7.2. clock suspension during burst write (using ck e) (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t2 2 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq t ck2 rax rax cax hi -z dax0 activate c om ma nd bank a write c om ma nd bank a cl oc k su sp en d 2 cycl es cl oc k su sp en d 3 cycl es dax1 dax2 dax3 cl oc k su sp en d 1 cyc le note: cke to clk disable/enable = 1 clock
etrontech em638165 preliminary 29 rev 0 .6 feb. 2001 figure 7.3. clock suspension during burst write (using cke) (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 - a 9 , a 1 1 dq m dq dax0 dax1 dax2 dax3 t ck3 rax rax cax hi -z activate c om ma nd bank a write c om ma nd bank a cl oc k su sp en d 2 cycl es cl oc k su sp en d 3 cycl es cl oc k su sp en d 1 cyc le note: cke to clk disable/enable = 1 clock
etrontech em638165 preliminary 30 rev 0 .6 feb. 2001 figure 8. power down mode and clock mask (burst lenght=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # b a0 ,1 a 1 0 a 0 ~ a 9 , a 1 1 dq m dq t ck2 t i s t pde rax rax cax t hz ax3 ax2 ax1 ax0 activate c om ma nd bank a po we r d own mode entry po we r d own mode exit r e ad c om ma nd bank a cloc k mask start cloc k mask e n d pr ec ha rge c om ma nd bank a po we r d own mode entry pre char ge stan dby any c om ma nd po we r d own mode exit hi -z val id active stan dby
etrontech em638165 preliminary 31 rev 0 .6 feb. 2001 figure 9.1. random column read (page within same bank) (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a r e ad c om ma nd bank a r e ad c om ma nd bank a pr ec ha rge c om ma nd bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay r e ad c om ma nd bank a hi -z caz az0 az1 az2 az3 r e ad c om ma nd bank a activate c om ma nd bank a raz raz
etrontech em638165 preliminary 32 rev 0 .6 feb. 2001 figure 9.2. random column read (page within same bank) (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a r e ad c om ma nd bank a r e ad c om ma nd bank a pr ec ha rge c om ma nd bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay r e ad c om ma nd bank a hi -z caz az0 az1 az2 az3 r e ad c om ma nd bank a activate c om ma nd bank a raz raz
etrontech em638165 preliminary 33 rev 0 .6 feb. 2001 figure 9.3. random column read (page within same bank) (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a r e ad c om ma nd bank a r e ad c om ma nd bank a pr ec ha rge c om ma nd bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 raw raw caw cax cay r e ad c om ma nd bank a hi -z caz r e ad c om ma nd bank a activate c om ma nd bank a raz raz az0
etrontech em638165 preliminary 34 rev 0 .6 feb. 2001 figure 10.1. random column write (page within same bank) (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a write c om ma nd bank a write c om ma nd ban k b pr ec ha rge c om ma nd ban k b db w0 db w1 db w2 db w3 dbx0 dbx1 db y0 db y1 db y2 db y3 rb w rb w cb w cbx cby write c om ma nd ban k b hi -z cbz db z0 db z1 db z2 db z3 write c om ma nd ban k b activate c om ma nd ban k b rbz rbz
etrontech em638165 preliminary 35 rev 0 .6 feb. 2001 figure 10.2. random column write (page within same bank) (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a write c om ma nd ban k b write c om ma nd ban k b pr ec ha rge c om ma nd ban k b db w0 db w1 db w2 db w3 dbx0 dbx1 db y0 db y1 db y2 db y3 rb w rb w cb w cbx cby write c om ma nd ban k b hi -z cbz db z0 db z1 db z2 db z3 write c om ma nd ban k b activate c om ma nd ban k b rbz rbz
etrontech em638165 preliminary 36 rev 0 .6 feb. 2001 figure 10.3. random column write (page within same bank) (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a write c om ma nd ban k b write c om ma nd ban k b pr ec ha rge c om ma nd ban k b db w0 db w1 db w2 db w3 dbx0 dbx1 db y0 db y1 db y2 db y3 rb w rb w cb w cbx cby write c om ma nd ban k b hi -z cbz db z0 db z1 write c om ma nd ban k b activate c om ma nd ban k b rbz rbz db z2
etrontech em638165 preliminary 37 rev 0 .6 feb. 2001 figure 11.1. random row read (interleaving banks) (burst length=8, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd ban k b activate c om ma nd bank a pr ec ha rge c om ma nd ban k b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby r e ad c om ma nd ban k b hi -z cby r e ad c om ma nd ban k b pr ec ha rge c om ma nd bank a hi gh rax r e ad c om ma nd bank a activate c om ma nd ban k b by0 by1 by2 ax2 ax3 ax4 ax5 ax6 ax7 cbx cax rax rby t rcd t ac1 t rp
etrontech em638165 preliminary 38 rev 0 .6 feb. 2001 figure 11.2. random row read (interleaving banks) (burst length=8, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd ban k b activate c om ma nd bank a pr ec ha rge c om ma nd ban k b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby r e ad c om ma nd ban k b hi -z cby r e ad c om ma nd ban k b hi gh rax r e ad c om ma nd bank a activate c om ma nd ban k b by0 by1 ax2 ax3 ax4 ax5 ax6 ax7 cbx cax rax rby t rcd t ac2 t rp
etrontech em638165 preliminary 39 rev 0 .6 feb. 2001 figure 11.3. random row read (interleaving banks) (burst length=8, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd ban k b activate c om ma nd bank a pr ec ha rge c om ma nd ban k b bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 rbx rbx rby r e ad c om ma nd ban k b hi -z cby r e ad c om ma nd ban k b hi gh rax r e ad c om ma nd bank a activate c om ma nd ban k b ax7 by0 ax2 ax3 ax4 ax5 ax6 cbx cax rax rby t rcd t ac3 t rp pr ec ha rge c om ma nd bank a
etrontech em638165 preliminary 40 rev 0 .6 feb. 2001 f igure 12.1. random row write (interleaving banks) (burst length=8, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a activate c om ma nd ban k b pr ec ha rge c om ma nd bank a dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray write c om ma nd bank a hi -z cay hi gh rbx pr ec ha rge c om ma nd ban k b dbx7 day3 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd day0 day1 day2 write c om ma nd bank a write c om ma nd ban k b activate c om ma nd bank a t rp t wr
etrontech em638165 preliminary 41 rev 0 .6 feb. 2001 figure 12.2. random row write (interleaving banks) (burst length=8, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a activate c om ma nd ban k b pr ec ha rge c om ma nd bank a dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray write c om ma nd bank a hi -z cay hi gh rbx pr ec ha rge c om ma nd ban k b dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd write c om ma nd bank a write c om ma nd ban k b activate c om ma nd bank a day3 day0 day1 day2 day4 t wr* t rp t wr* * t wr > t wr (m in.)
etrontech em638165 preliminary 42 rev 0 .6 feb. 2001 figure 12.3. random row write (interleaving banks) (burst length=8, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a activate c om ma nd ban k b pr ec ha rge c om ma nd bank a dax0 dax1 dax2 dax3 dax4 dax5 dax6 dax7 dbx0 dbx1 rax rax ray write c om ma nd bank a hi -z cay hi gh rbx pr ec ha rge c om ma nd ban k b dbx7 dbx2 dbx3 dbx4 dbx5 dbx6 cax cbx rbx ray t rcd write c om ma nd bank a write c om ma nd ban k b activate c om ma nd bank a day3 day0 day1 day2 t wr* t rp t wr* * t wr > t wr (min.)
etrontech em638165 preliminary 43 rev 0 .6 feb. 2001 figure 13.1. read and write cycle (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a the write data is m asked with a zer o cl ock la ten cy r e ad c om ma nd bank a ax0 ax1 ax2 ax3 day0 day1 hi -z pr ec ha rge c om ma nd ban k b az3 day3 az0 az1 r e ad c om ma nd bank a write c om ma nd bank a the rea d da ta is m asked with a two clock la ten cy rax rax cax cay caz
etrontech em638165 preliminary 44 rev 0 .6 feb. 2001 fig ure 13.2. read and write cycle (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a the write data is m asked with a zer o cl ock la ten cy r e ad c om ma nd bank a ax0 ax1 ax2 ax3 day0 day1 hi -z az3 day3 az0 az1 r e ad c om ma nd bank a write c om ma nd bank a the rea d da ta is m asked with a two clock la ten cy rax rax cax cay caz
etrontech em638165 preliminary 45 rev 0 .6 feb. 2001 figure 13.3. read and write cycle (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a the write data is m asked with a zer o cl ock la ten cy r e ad c om ma nd bank a ax0 ax1 ax2 ax3 day0 day1 hi -z az3 day3 az0 az1 r e ad c om ma nd bank a write c om ma nd bank a the rea d da ta is m asked with a two clock la ten cy rax rax cax cay caz
etrontech em638165 preliminary 46 rev 0 .6 feb. 2001 figure 14.1. interleaving column read cycle (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a r e ad c om ma nd ban k b pr ec ha rge c om ma nd bank a bw 0 bw 1 bx0 bx1 by1 ay0 hi -z bz0 r e ad c om ma nd bank a r e ad c om ma nd bank a rax rax ax0 ax1 ax2 ax3 by0 ay1 bz1 bz2 bz3 activate c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd ban k b pr ec ha rge c om ma nd ban k b t rcd t ac1 rax rb w rb w cb w cbx cby cay cbz
etrontech em638165 preliminary 47 rev 0 .6 feb. 2001 figure 14.2. interleaving column read cycle (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a r e ad c om ma nd ban k b pr ec ha rge c om ma nd bank a bw 0 bw 1 bx0 bx1 by1 ay0 hi -z bz0 r e ad c om ma nd bank a r e ad c om ma nd bank a rax rax ax0 ax1 ax2 ax3 by0 ay1 bz1 bz2 bz3 activate c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd ban k b pr ec ha rge c om ma nd ban k b t rcd t ac2 cay rax rax cb w cbx cby cay cbz
etrontech em638165 preliminary 48 rev 0 .6 feb. 2001 figure 14.3. interleaved column read cycle (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a pr ec ha er ge c om ma nd ban k b bx0 bx1 by0 by1 bz1 ay0 hi -z ay2 r e ad c om ma nd bank a r e ad c om ma nd bank a rax rax ax0 ax1 ax2 ax3 bz0 ay1 ay3 activate c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd ban k b pr ec ha rge c om ma nd bank a t rcd t ac3 cax rbx rbx cbx cby cbz cay
etrontech em638165 preliminary 49 rev 0 .6 feb. 2001 figure 15.1. interleaved column write cycle (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a write c om ma nd ban k b db w0 db w1 dbx0 dbx1 db y1 day0 hi -z write c om ma nd bank a pr ec ha rge c om ma nd bank a rax rax dax0 dax1 dax2 dax3 db y0 day1 db z0 activate c om ma nd ban k b write c om ma nd ban k b write c om ma nd ban k b write c om ma nd bank a pr ec ha rge c om ma nd ban k b t rcd cax rb w rb w cb w cbx cby cay db z1 db z2 db z3 write c om ma nd ban k b t rrd t rp t wr t rp cbz t6
etrontech em638165 preliminary 50 rev 0 .6 feb. 2001 figure 15.2. interleaved column write cycle (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a write c om ma nd ban k b db w0 db w1 dbx0 dbx1 db y1 day0 hi -z write c om ma nd bank a pr ec ha rge c om ma nd bank a rax rax dax0 dax1 dax2 dax3 db y0 day1 db z0 activate c om ma nd ban k b write c om ma nd ban k b write c om ma nd ban k b write c om ma nd bank a pr ec ha rge c om ma nd ban k b t rcd cax rb w rb w cb w cbx cby cay db z1 db z2 db z3 write c om ma nd ban k b t rrd t rp t wr t rp cbz we #
etrontech em638165 preliminary 51 rev 0 .6 feb. 2001 figure 15.3. interleaved column write cycle (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a write c om ma nd ban k b db w0 db w1 dbx0 dbx1 db y1 day0 hi -z write c om ma nd bank a pr ec ha rge c om ma nd bank a rax rax dax0 dax1 dax2 dax3 db y0 day1 db z0 activate c om ma nd ban k b write c om ma nd ban k b write c om ma nd ban k b write c om ma nd bank a pr ec ha rge c om ma nd ban k b t rcd cax rb w rb w cb w cbx cby cay db z1 db z2 db z3 write c om ma nd ban k b t rrd > t rrd(min) t rp t wr t wr(min) cbz we #
etrontech em638165 preliminary 52 rev 0 .6 feb. 2001 figure 16.1. auto precharge after read burst (burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a activate c om ma nd ban k b bx0 bx1 bx2 bx3 ay1 ay2 hi -z r e ad c om ma nd bank a rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 activate c om ma nd ban k b activate c om ma nd ban k b rbx cbx cay rby cby by1 by2 by3 rbz hi gh bz0 bz1 bz2 bz3 re ad w ith au to p rech arge c om ma nd ban k b re ad w ith au to p rech arge c om ma nd bank a re ad w ith au to p rech arge c om ma nd ban k b re ad w ith au to p rech arge c om ma nd ban k b cax rby rbz cbz
etrontech em638165 preliminary 53 rev 0 .6 feb. 2001 figure 16.2. auto pre charge after read burst (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a activate c om ma nd bank a bx0 bx1 bx2 bx3 ay1 ay2 hi -z r e ad c om ma nd bank a rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 activate c om ma nd ban k b activate c om ma nd ban k b rbx cbx rby ray cby by1 by2 by3 hi gh az0 az1 az2 re ad w ith au to p rech arge c om ma nd ban k b re ad w ith au to p rech arge c om ma nd bank a re ad w ith au to p rech arge c om ma nd ban k b re ad w ith au to p rech arge c om ma nd bank a cax rby raz caz raz
etrontech em638165 preliminary 54 rev 0 .6 feb. 2001 figure 16.3. auto precharge after read burst (burst length=4, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a bx0 bx1 bx2 bx3 ay1 ay2 hi -z r e ad c om ma nd bank a rax rax rbx ax0 ax1 ax2 ax3 ay0 ay3 by0 activate c om ma nd ban k b activate c om ma nd ban k b rbx cbx by1 by2 by3 hi gh re ad w ith au to p rech arge c om ma nd ban k b re ad w ith au to p rech arge c om ma nd bank a re ad w ith au to p rech arge c om ma nd ban k b cax rby cby rby cay we #
etrontech em638165 preliminary 55 rev 0 .6 feb. 2001 figure 17.1. auto precharge after write burst ( burst length=4, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 activate c om ma nd bank a dbx0 dbx1 dbx2 dbx3 day1 day2 hi -z write c om ma nd bank a rax rax rbx dax0 dax1 dax2 dax3 day0 day3 db y0 activate c om ma nd ban k b activate c om ma nd ban k b cbx cay db y1 db y2 db y3 hi gh write with au to p rech arge c om ma nd ban k b write with au to p rech arge c om ma nd bank a write with au to p rech arge c om ma nd ban k b rby caz cby rby daz0 daz0 activate c om ma nd bank a write with au to p rech arge c om ma nd bank a daz0 daz0 cax rbx raz raz t 1 1
etrontech em638165 preliminary 56 rev 0 .6 feb. 2001 figure 17.2. auto precharge after write burst (burst length=4, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 activate c om ma nd bank a dbx0 dbx1 dbx2 dbx3 day1 day2 hi -z write c om ma nd bank a rax rax rbx dax0 dax1 dax2 dax3 day0 day3 db y0 activate c om ma nd ban k b activate c om ma nd ban k b cbx cay db y1 db y2 db y3 hi gh write with au to p rech arge c om ma nd ban k b write with au to p rech arge c om ma nd bank a write with au to p rech arge c om ma nd ban k b rby cby rby daz0 daz1 activate c om ma nd bank a write with au to p rech arge c om ma nd bank a daz2 daz3 cax rbx caz raz raz we #
etrontech em638165 preliminary 57 rev 0 .6 feb. 2001 figure 17.3. auto precharge after write burst (burst length=4, cas# lat ency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 9 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 activate c om ma nd bank a dbx0 dbx1 dbx2 dbx3 day1 day2 hi -z write c om ma nd bank a rax rax rbx dax0 dax1 dax2 dax3 day0 day3 db y0 activate c om ma nd ban k b activate c om ma nd ban k b cbx db y1 db y2 db y3 hi gh write with au to p rech arge c om ma nd ban k b write with au to p rech arge c om ma nd bank a write with au to p rech arge c om ma nd ban k b cay cax rbx cby rby rby `
etrontech em638165 preliminary 58 rev 0 .6 feb. 2001 figure 18.1. full page read cycle (burst length=full page, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 activate c om ma nd bank a a x ax +1 bx bx +1 bx +3 bx +4 hi -z r e ad c om ma nd bank a rax rax rbx ax +1 ax +2 ax-2 ax-1 bx +2 bx +5 activate c om ma nd ban k b burst stop c om ma nd cbx hi gh r e ad c om ma nd ban k b pr ec ha rge c om ma nd ban k b cax rbx rby rby a x bx +6 bx +7 the bur st co unte r wr aps fro m th e hi ghes t or der pa ge a ddre ss back to zero du ring th is t ime in terv al fu ll pag e bu rst op era tio n d oes not ter mina te w hen the burst len gth is s atis fied; th e bu rst co unte r i ncre men ts a nd con tinu es bu rst in g b egi nni ng wi th the s tar tin g a dd res s. activate c om ma nd ban k b t ck1 t rrd t rp
etrontech em638165 preliminary 59 rev 0 .6 feb. 2001 figure 18.2. full page read cycle (burst length=full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 activate c om ma nd bank a a x ax +1 bx bx +1 bx +3 bx +4 hi -z r e ad c om ma nd bank a rax rax ax +1 ax +2 ax-2 ax-1 bx +2 bx +5 activate c om ma nd ban k b burst stop c om ma nd cbx hi gh r e ad c om ma nd ban k b pr ec ha rge c om ma nd ban k b rbx cax rby rby a x bx +6 the bur st co unte r wr aps fro m th e hi ghes t or der pa ge a ddre ss back to zero du ring th is t ime in terv al fu ll pag e bu rst op era tio n d oes not ter mina te w hen the burst len gth is s atis fied; th e bu rst co unte r i ncre men ts a nd con tinu es bu rst in g b egi nni ng wi th the s tar tin g a dd res s. activate c om ma nd ban k b t ck2 t rp rbx
etrontech em638165 preliminary 60 rev 0 .6 feb. 2001 figure 18.3. full page read cycle (burst length=full page, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 activate c om ma nd bank a a x ax +1 bx bx +1 bx +3 bx +4 hi -z r e ad c om ma nd bank a rax rax ax +1 ax +2 ax-2 ax-1 bx +2 bx +5 activate c om ma nd ban k b burst stop c om ma nd cbx hi gh r e ad c om ma nd ban k b pr ec ha rge c om ma nd ban k b rbx cax rby rby a x the bur st co unte r wr aps fro m th e hi ghes t or der pa ge a ddre ss back to zero du ring th is t ime in terv al fu ll pag e bu rst op era tio n d oes not te rmin ate whe n t he b urs t le ngt h is sat isfied ; the burs t coun ter in cre me nts an d con tin ues bu rs ti ng b eg in ni ng w it h the sta rtin g ad dres s. activate c om ma nd ban k b t ck3 t rp rbx
etrontech em638165 preliminary 61 rev 0 .6 feb. 2001 figure 19.1. full page write cycle (burst length=full page, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 d a x + 1 dax activate c om ma nd bank a hi -z activate c om ma nd ban k b rax rax burst stop c om ma nd cbx hi gh write c om ma nd ban k b pr ec ha rge c om ma nd ban k b rbx cax rby rby the bur st co unte r wr aps fro m th e hi ghes t or der pa ge a ddre ss back to zero du ring th is t ime in terv al fu ll pag e b urs t ope rat ion do es not ter mina te w hen the burst len gth is s atisf ied; the burs t co unter in cre me nts an d con tin ue s b urs ti ng be gin nin g wit h t he sta rt ing ad dre ss. activate c om ma nd ban k b t ck1 d a x + 2 d a x + 3 d a x - 1 dax d a x + 1 dbx d b x + 1 d b x + 2 d b x + 3 d b x + 4 d b x + 5 d b x + 6 d b x + 7 write c om ma nd bank a da ta is ig nor ed rbx
etrontech em638165 preliminary 62 rev 0 .6 feb. 2001 figure 19.2. full page write cycle (burst length=full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 d a x + 1 dax activate c om ma nd bank a hi -z activate c om ma nd ban k b rax rax burst stop c om ma nd cbx hi gh write c om ma nd ban k b pr ec ha rge c om ma nd ban k b rbx cax rby rby the bur st co unte r wr aps fro m th e hi ghes t or der pa ge a ddre ss back to zero du ring th is t ime in terv al fu ll pag e b urs t ope rat ion do es not ter mina te w hen the burst len gth is s atisf ied; the burs t co unter in cre me nts an d con tin ue s b urs ti ng be gin nin g wit h t he sta rt ing ad dre ss. activate c om ma nd ban k b t ck2 d a x + 2 d a x + 3 d a x - 1 dax d a x + 1 dbx d b x + 1 d b x + 2 d b x + 3 d b x + 4 d b x + 5 d b x + 6 write c om ma nd bank a da ta is ig nor ed rbx
etrontech em638165 preliminary 63 rev 0 .6 feb. 2001 figure 19.3. full page write cycle (burst length=full page, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 d a x + 1 dax activate c om ma nd bank a hi -z activate c om ma nd ban k b rax rax burst stop c om ma nd cbx hi gh rbx cax write c om ma nd ban k b pr ec ha rge c om ma nd ban k b rby rby the bur st co unte r wr aps fro m th e hi ghes t or der pa ge a ddre ss back to zero du ring th is t ime in terv al fu ll pag e b urs t ope rat ion do es not ter mina te w hen the burst len gth is s atisf ied; the burs t co unter in cre me nts an d con tin ue s b urs ti ng be gin nin g wit h t he sta rt ing ad dre ss. activate c om ma nd ban k b t ck3 rbx d a x + 2 d a x + 3 d a x - 1 dax d a x + 1 dbx d b x + 1 d b x + 2 d b x + 3 d b x + 4 d b x + 5 write c om ma nd bank a da ta is ig nor ed
etrontech em638165 preliminary 64 rev 0 .6 feb. 2001 figure 20. byte write operation (burst length=4 , cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 ld qm u d q m b a0 ,1 rax rax cay hi gh cax t ck2 caz activate c om ma nd bank a r e ad c om ma nd bank a upp er 3 bytes ar e ma sked write c om ma nd bank a upp er 3 bytes ar e ma sked r e ad c om ma nd bank a lowe r byte is mask ed lowe r byte is mask ed lowe r byte is mask ed ax0 ax1 ax2 ax1 ax2 ax3 day1 day2 day0 day1 day3 az1 az2 az1 az2 az0 az3 dq0 - dq7 dq 8 - dq15
etrontech em638165 preliminary 65 rev 0 .6 feb. 2001 figure 21. random row read (interleaving banks) (burst length=2, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 hi gh t ck1 b u0 b u1 au 0 au 1 bv0 bv1 av0 av1 bw 0 bw 1 aw0 aw1 bx0 bx1 ax0 ax1 by0 by1 ay0 ay1 bz0 activate c om ma nd ban k b r e ad ban k b wit h auto pr ec ha rge activate c om ma nd bank a r e ad bank a wit h auto pr ec ha rge activate c om ma nd ban k b r e ad ban k b wit h auto pr ec ha rge activate c om ma nd bank a r e ad bank a wit h auto pr ec ha rge activate c om ma nd ban k b r e ad ban k b wit h auto pr ec ha rge activate c om ma nd bank a r e ad bank a wit h auto pr ec ha rge activate c om ma nd ban k b r e ad ban k b wit h auto pr ec ha rge activate c om ma nd bank a r e ad bank a wit h auto pr ec ha rge activate c om ma nd ban k b r e ad ban k b wit h auto pr ec ha rge activate c om ma nd bank a r e ad bank a wit h auto pr ec ha rge activate c om ma nd ban k b r e ad ban k b wit h auto pr ec ha rge activate c om ma nd bank a r bu r bu c bu ra u ra u ca u rbv rbv cbv rav rav cav rb w rb w cb w raw raw caw rbx rbx cbx rax rax cax rby rby cby ray ray cay rbz rbz cbz raz raz t rp t rp t rp t rp t rp t rp t rp t rp t rp t rp be gin au to pr ec ha rge ban k b be gin au to pr ec ha rge bank a be gin au to pr ec ha rge ban k b be gin au to pr ec ha rge bank a be gin au to pr ec ha rge ban k b be gin au to pr ec ha rge bank a be gin au to pr ec ha rge ban k b be gin au to pr ec ha rge bank a be gin au to pr ec ha rge ban k b be gin au to pr ec ha rge bank a
etrontech em638165 preliminary 66 rev 0 .6 feb. 2001 figure 22. full page random column read (burst length=full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 ax0 bx0 ay0 ay1 by0 by1 az0 az1 az2 bz0 bz1 bz2 activate c om ma nd bank a r e ad c om ma nd bank a activate c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd ban k b r e ad c om ma nd bank a r e ad c om ma nd ban k b pr ec ha rge co mma nd b ank b (p rech arg e te min atio n) t rp r e ad c om ma nd bank a activate c om ma nd ban k b t rrd t rcd rax rax rbx rbx cax cbx cay cby caz cbz rb w rb w
etrontech em638165 preliminary 67 rev 0 .6 feb. 2001 figure 23. full page random column write (burst length=full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 dax0 dbx0 day0 day1 db y0 db y1 daz0 daz1 daz2 db z0 db z1 db z2 activate c om ma nd bank a write c om ma nd bank a activate c om ma nd ban k b write c om ma nd ban k b write c om ma nd ban k b write c om ma nd bank a write c om ma nd ban k b pr ec ha rge co mma nd b ank b (p rech arg e te min atio n) t rp write c om ma nd bank a activate c om ma nd ban k b t rrd t rcd rax rax rbx rbx cax cbx cay cby caz cbz rb w rb w t wr write data is mask ed
etrontech em638165 preliminary 68 rev 0 .6 feb. 2001 figure 24.1. precharge termination of a burst (burst length=full page, cas# latency=1) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck1 dax0 dax1 dax2 dax3 dax4 ay0 ay1 ay2 daz3 daz2 daz0 activate c om ma nd bank a write c om ma nd bank a pr ec ha rge c om ma nd bank a r e ad c om ma nd bank a pr ec ha rge c om ma nd bank a write c om ma nd bank a rax rax ray cax ray cay raz daz1 daz4 daz5 daz6 daz7 pr echa rge te rmin ati on of a write burst. write data is ma sked. activate c om ma nd bank a activate c om ma nd bank a t wr t rp t rp pr ec ha rge ter minat ion of a re ad bur st. raz caz
etrontech em638165 preliminary 69 rev 0 .6 feb. 2001 figure 24.2. precharge termination of a burst (burst length=8 or full page, cas# latency=2) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck2 dax0 dax1 dax2 dax3 ay2 ay0 ay1 activate c om ma nd bank a write c om ma nd bank a pr ec ha rge c om ma nd bank a r e ad c om ma nd bank a pr ec ha rge c om ma nd bank a activate c om ma nd bank a rax rax ray cax ray cay az0 az1 az2 pr echa rge te rmin ati on of a write burst. write data is ma sked. activate c om ma nd bank a t wr t rp t rp raz caz hi gh r e ad c om ma nd bank a pr ec ha rge c om ma nd bank a pr echa rge te rmin ati on of a read b urst t rp raz
etrontech em638165 preliminary 70 rev 0 .6 feb. 2001 figure 24.3. precharge termination of a burst (burst length=4, 8 or full page, cas# latency=3) t0 t 1 t2 t3 t4 t5 t6 t7 t8 t9 t 10 t 1 1 t 12 t 13 t 14 t 15 t 16 t 17 t 18 t 19 t 20 t 21 t 22 cl k cke cs # r as # c a s# we # a 1 0 a 0 ~ a 9 , a 1 1 dq m dq b a0 ,1 t ck3 dax0 ay0 ay1 ay2 activate c om ma nd bank a write c om ma nd bank a pr echa rge te rmin ati on of a write burst r e ad c om ma nd bank a pr ec ha rge c om ma nd bank a rax rax ray cax ray cay write data is mask ed activate c om ma nd bank a t wr t rp t rp raz raz hi gh activate c om ma nd bank a pr ec ha rge c om ma nd bank a pr echa rge te rmin ati on of a read b urst dax1
etrontech em638165 preliminary 71 rev 0 .6 feb. 2001 54 pin tsop ii package outline drawing information y s b e a a 1 a 2 l l 1 c 5 4 1 d e h e 0. 2 54 q l l 1 2 7 2 8 symbol dimension in inch dimension in mm min normal max min normal max a - - 0.047 - - 1.194 a1 0.002 0.00395 0.0059 0.05 0.1 0. 150 a2 - - 0.0411 - - 1.044 b 0.012 0.015 0.016 0.3 0.35 0.40 c 0.0047 0.0065 0.0083 0.120 1.165 0.210 d 0.872 0.8755 0.879 22.149 22.238 22.327 e 0.3960 0.400 0.4040 10.058 10.16 10.262 e - 0.0315 - - 0.80 - he 0.462 0.466 0.470 11.735 11.8365 11.938 l 0.016 0.020 0.0235 0.406 0.50 0.597 l1 - 0.033 - - 0.84 - s - 0.035 - - 0.88 - y - - 0.004 - - 0.10 q 0 - 5 0 - 5 notes: 1. dimension d&e do not include interiead flash. 2. dimension b does not include dambar p rotrusion/intrusion. 3. dimension s includes end flash. 4. controlling dimension : mm

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